The subject matter of the present invention relates generally to circuitry for converting CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS circuits to ECL circuits and to a means for temperature compensating such circuitry.
To couple a CMOS circuit to an ECL circuit the difference between the output voltages from the one circuit and the input voltages needed by the second circuit must be generated by some form of interfacing circuit. A CMOS circuit's logic level "1" will approach the power supply value, generally 3 volts, while its logic level "0" will be near the reference or ground level. On the other hand, an ECL circuit's logic level "1" will approach -0.8 volts while its logic level "0" will approach -1.68 volts. If the interfacing circuit derives its power from the CMOS circuit the difference in temperature between the CMOS and the ECL circuit can cause a variance in the response level of the ECL circuit due to the shifts in electrical characteristics as a function of temperature. In order to minimize and/or to totally eliminate the temperature sensitivity of the interfacing circuit it would be preferable to have a means for temperature compensating the interfacing circuit to the ECL circuit such that the output from the interfacing circuit fluctuates in the same and/or similar manner as the sensitivity of the input(s) to the ECL circuits.
Circuitry for performing an interfacing function is shown in U.S. Pat. No. 4,486,671, entitled "Voltage Level Shifting Circuit", by Daniel Ong. The circuit described in that patent is a voltage level shifting circuit that is suitable as an interface circuit between TTL and CMOS circuitry.
Another patent of interest is U.S. Pat. No. 4,486,670, entitled "Monolithic CMOS Low Power Digital Level Shifter", by Yiu-Fai Chan et al. The circuit of that patent provides a power level shift which converts the typical transistor logic levels, for example, typically 5 volts to a higher voltage, approximately 20 volts, in order to program an EPROM.
Another patent of interest is U.S. Pat. No. 4,453,095, entitled "ECL MOS Buffer Circuits", by R. S. Wrathall. The circuit of that patent is a buffer circuit for interfacing CMOS circuitry with associated ECL devices. One relevant interfacing inverter circuit is shown, for example, in FIG. 1B.
In U.S. Pat. No. 3,716,722 entitled "Temperature Compensation for Logic Circuits," by R. W. Bryant et al., there is disclosed a temperature compensating circuit for ECL circuits mounted on a single chip or on different chips connected to each other.
In U.S. Pat. No. 3,806,736 entitled "Temperature Compensated Emitter Coupled Logic Circuit," by W. Wilhelm, there is disclosed a temperature compensated ECL circuit incorporating a differential amplifier.
In U.S. Pat. No. 4,461,992 entitled "Temperature-Compensated Current Source Circuit and a Reference Voltage Generating Circuit Using the Same," by K. Y. Sayama et al., there is disclosed a circuit which combines the current flow from a positive temperature dependent path with the current flow from a negative temperature dependent path to substantially cancel the effects of temperature.
In U.S. Pat. No. 4,533,842 entitled "Temperature Compensated TTL to ECL Translator," by T-S Yang et al., there is disclosed a level translator for converting TTL logic levels to ECL logic levels incorporating a temperature compensating circuit which selects resistor ratios so as to offset negative temperature coefficients with positive temperature coefficients thereby nulling the effect of temperature on the circuit.